Cache circuitry, data processing apparatus and method for handling write access requests
US7600077B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 10, 2007 |
| Grant date | Oct 6, 2009 |
| Priority date | — |
| Expiry date | Mar 22, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1027
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Cache circuitry, a data processing apparatus including such cache circuitry, and a method of handling write requests within cache circuitry, are provided. The cache circuitry has a plurality of slots, with each slot arranged to store attributes associated with a pending access request. A record of identifiers that are available to associate with pending access requests is maintained, and control circuitry is responsive to an access request issued by a device to accept that access request as a pending access request by allocating one of the slots to that access request, obtaining one of said identifiers from the record to associate with that access request, and causing the attributes associated with that access request to be stored in the allocated slot along with the obtained identifier. A check procedure is performed to determine, for each pending access request, whether that access request is allowed to proceed. For a speculative pending write access request that is determined to be allowed to proceed, the attributes associated with that access request and the identifier associated with that access request are transferred from the allocated slot to a write entry within a write ac…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.