Integrated circuit conserving power during transitions between normal and power-saving modes
US7600142B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 21, 2006 |
| Grant date | Oct 6, 2009 |
| Priority date | — |
| Expiry date | Jun 8, 2027 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes a volatile memory, a central processing unit that normally operates on a first clock, and an input-output circuit that transfers data in synchronization with a second clock having a lower frequency than the first clock. The integrated circuit has a power-saving mode in which the volatile memory loses its data and the central processing unit stops operating. The power-saving mode is preceded and followed by transitional periods during which the central processing unit uses the input-output circuit to save data from the volatile memory to an external memory device and restore the data from the external memory device to the volatile memory. During these transitional periods, the central processing unit operates on the second clock to conserve power.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.