Method for reducing the trap density in a semiconductor wafer
US7601606B2 · kind B2 · utility
2Cited by
8References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 28, 2006 |
| Grant date | Oct 13, 2009 |
| Priority date | — |
| Expiry date | Aug 23, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28167
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention provides methods for reducing trap densities at interfaces in a multilayer semiconductor wafer, specifically trap densities between an active layer and an insulating layer under the active layer. The methods comprise exposing wafers to high temperatures in a generally neutral atmosphere that also comprises one or more species that can, or whose ions can, migrate into the wafer down to the interface where reduction of the trap density is desired.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.