Memory array buried digit line
US7601608B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 21, 2006 |
| Grant date | Oct 13, 2009 |
| Priority date | — |
| Expiry date | Jul 21, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/34
Abstract
A method of forming a buried digit line is disclosed. Sacrificial spacers are formed along the sidewalls of an isolation trench, which is then filled with a sacrificial material. One spacer is masked while the other spacer is removed and an etch step into the substrate beneath the removed spacer forms an isolation window. Insulating liners are then formed along the sidewalls of the emptied trench, including into the isolation window. A digit line recess is then formed through the bottom of the trench between the insulating liners, which double as masks to self-align this etch. The digit line recess is then filled with metal and recessed back, with an optional prior insulating element deposited and recessed back in the bottom of the recess.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.