Method for fabricating an integrated gate dielectric layer for field effect transistors

US7601648B2 · kind B2 · utility

Assignee

• Applied Materials, Inc. · US

Inventors

• Thai Cheng Chua · Cupertino, US
• Shankar Muthukrisnan · Plano, US
• Johanes F. Swenberg · Los Gatos, US
• Shreyas Kher · Campbell, US
• Chikuang Charles Wang · Santa Clara, US
• Giuseppina Conti · Oakland, US
• Yuri S. Uritsky · Newark, US

Key dates

• Filing date: Jul 31, 2006
• Grant date: Oct 13, 2009
• Expiry date: Mar 22, 2027

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/02301
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Methods for forming a integrated gate dielectric layer on a substrate are provided. In one embodiment, the method includes forming a silicon oxide layer on a substrate, plasma treating the silicon oxide layer, depositing a silicon nitride layer on the silicon oxide layer by an ALD process, and thermal annealing the substrate. In another embodiment, the method includes precleaning a substrate, forming a silicon oxide layer on the substrate, plasma treating the silicon oxide layer, depositing a silicon nitride layer on the silicon oxide layer by an ALD process, and thermal annealing the substrate, wherein the formed silicon oxide layer and the silicon nitride layer has a total thickness less than 30 Å utilized as a gate dielectric layer in a gate structure.