Transistor and method of manufacturing the same
US7601983B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 19, 2005 |
| Grant date | Oct 13, 2009 |
| Priority date | — |
| Expiry date | Aug 27, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/021
Abstract
A transistor includes a semiconductor substrate that has a first surface of a {100} crystal plane, a second surface of the {100} crystal plane having a height lower than that of the first surface, and a third surface of a {111} crystal plane connecting the first surface to the second surface. First heavily doped impurity regions are formed under the second surface. A gate structure is formed on the first surface. An epitaxial layer is formed on the second surface and the third surface. Second heavily doped impurity regions are formed at both sides of the gate structure. The second heavily doped impurity regions have side faces of the {111} crystal plane so that a short channel effect generated between the impurity regions may be prevented.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.