Short channel LV, MV, and HV CMOS devices

US7602017B2 · kind B2 · utility

Assignee

• FAIRCHILD SEMICONDUCTOR CORPORATION · US

Inventor

• Jun Cai · Allen, US

Key dates

• Filing date: Mar 13, 2007
• Grant date: Oct 13, 2009
• Expiry date: Mar 20, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/0212

Abstract

Low voltage, middle voltage and high voltage CMOS devices have upper buffer layers of the same conductivity type as the sources and drains that extend under the sources and drains and the gates but not past the middle of the gates, and lower bulk buffer layers of the opposite conductivity type to the upper buffer layers extend from under the upper buffer layers to past the middle of the gates forming an overlap of the two bulk buffer layers under the gates. The upper buffer layers and the lower bulk buffer layers can be implanted for both the NMOS and PMOS FETs using two masking layers. For middle voltage and high voltage devices the upper buffer layers together with the lower bulk buffer layers provide a resurf region.