Voltage multiplier with improved efficiency
US7602233B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 29, 2008 |
| Grant date | Oct 13, 2009 |
| Priority date | — |
| Expiry date | Apr 5, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02M3/078
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A multi-stage voltage multiplication circuit and methodology are provided which use a multi-stage charge pump boosting circuit (210) and two-stage pass gate circuit (220) having complementary power switches (M6, M9, M7, M10) to efficiently develop an output voltage (VOUT) that is higher than the input supply voltage (VDD). By using a two-stage complementary switch to connect boosted clock signals (P1, P2) from a charge pump (210) to the multiplier output (VOUT), return current from the storage capacitor (COUT) to the pumping capacitor (C1, C2) is blocked, thereby increasing power transfer efficiency, even at high clock frequencies. In addition, a boosted auxiliary voltage is generated by an additional boosting stage (230) and applied to the PMOS wells of the pass gate circuit (220), thereby preventing latch-up and backflow.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.