Configurable memory architecture with built-in testing mechanism
US7603603B2 · kind B2 · utility
11Cited by
5References
27Claims
0Family size
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Key dates
| Filing date | May 26, 2006 |
| Grant date | Oct 13, 2009 |
| Priority date | — |
| Expiry date | Jul 30, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/3602
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A configurable memory architecture includes a built-in testing mechanism integrated in said memory to support very efficient built-in self-test in Random Access Memories (RAMs) with greatly reduced overhead, in terms of area and speed. Memories can fail at high speed due to glitches (unwanted pulses which can at times behave as invalid clocks and destroy the functionality of synchronous systems) produced in decoding, the slow precharge of bitlines or the slow sensing of the sense amplifiers. The memory architecture incorporates structured DFT techniques to separately detect these failures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.