Method and apparatus for power optimization using don't care conditions of configuration bits in lookup tables
US7603646B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 21, 2007 |
| Grant date | Oct 13, 2009 |
| Priority date | — |
| Expiry date | Jan 11, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various approaches for generating an implementation of an electronic circuit design are disclosed. In one approach, one or more configuration bits that have don't care conditions are identified for a LUT block of a design. A dynamic power state for a subset of a first level of logic devices in the LUT block is determined as a function of each identified configuration bit that has a don't care condition. A dynamic power state for a subset of a second level of logic devices is determined as a function of the determined power state for the first level of logic devices. A respective value for each identified configuration bit of the LUT is selected in response to the determined dynamic power states. The respective value is placed into the design for each identified configuration bit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.