Sub-lithographic feature patterning using self-aligned self-assembly polymers
US7605081B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 19, 2006 |
| Grant date | Oct 20, 2009 |
| Priority date | — |
| Expiry date | Jan 23, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/485
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for conducting sub-lithography feature patterning of a device structure is provided. First, a lithographically patterned mask layer that contains one or more mask openings of a diameter d is formed by lithography and etching over an upper surface of the device structure. Next, a layer of a self-assembling block copolymer is applied over the lithographically patterned mask layer and then annealed to form a single unit polymer block of a diameter w inside each of the mask openings, provided that w<d. Each single unit polymer block of the present invention is embedded in a polymeric matrix and can be selectively removed against the polymeric matrix to form a single opening of the diameter w in the polymeric matrix inside each of the mask openings. Sub-lithography feature patterning can then be conducted in the device structure using the single openings of diameter w.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.