Enhanced segmented channel MOS transistor with high-permittivity dielectric isolation material
US7605449B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 30, 2007 |
| Grant date | Oct 20, 2009 |
| Priority date | — |
| Expiry date | Nov 30, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
Abstract
By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repeatably produced. Forming a corrugated substrate prior to actual device formation allows the ridges on the corrugated substrate to be created using high precision techniques that are not ordinarily suitable for device production. MOSFETs that subsequently incorporate the high-precision ridges into their channel regions will typically exhibit much more precise and less variable performance than similar MOSFETs formed using optical lithography-based techniques that cannot provide the same degree of patterning accuracy. Additional performance enhancement techniques such as pulse-shaped doping, “wrapped” gates, epitaxially grown conductive regions, epitaxially grown high mobility semiconductor materials (e.g. silicon-germanium, germanium, gallium arsenide, etc.), high-permittivity ridge isolation material, and narrowed base regions can be used in conjunction with the segmented channel regions…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.