Coreless substrate and manufacturing thereof
US7605459B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 15, 2007 |
| Grant date | Oct 20, 2009 |
| Priority date | — |
| Expiry date | Mar 30, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18165
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An aspect of the present invention features a manufacturing method of a package on package with a cavity. The method can comprise (a) forming a first upper substrate cavity in one side of an upper substrate; (b) mounting an upper semiconductor chip on the other side of the upper substrate; (c) forming a lower substrate cavity in one side of a lower substrate; (d) mounting a lower semiconductor chip in the lower substrate cavity formed in the lower substrate; and (e) stacking the upper substrate above the lower substrate such that the first upper substrate cavity accommodates a part of the lower semiconductor chip. The package on package and a manufacturing method thereof can reduce the overall thickness of the package by forming cavities in both upper and lower substrates to accommodate a semiconductor chip mounted in the lower substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.