System for glitch-free delay updates of a standard cell-based programmable delay
US7605628B2 · kind B2 · utility
3Cited by
2References
20Claims
0Family size
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Key dates
| Filing date | May 7, 2007 |
| Grant date | Oct 20, 2009 |
| Priority date | — |
| Expiry date | Dec 24, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00234
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method for glitch-free updates of a standard cell-based programmable delay including the steps of (A) generating an output signal in response to an input signal and a plurality of first control signals and (B) generating the plurality of first control signals in response to the output signal and a plurality of second control signals. The output signal may include a delayed version of the input signal. An amount of delay between the input signal and the output signal may be determined based upon the plurality of first control signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.