Three-dimensional programmable resistance memory device with a read/write circuit stacked under a memory cell array
US7606059B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 18, 2003 |
| Grant date | Oct 20, 2009 |
| Priority date | — |
| Expiry date | Apr 26, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8825
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A programmable resistance memory device includes a semiconductor substrate, at least one cell array, in which memory cells are arranged and formed above the semiconductor substrate. Each of the memory cells has a stack structure of a programmable resistance element and an access element, the programmable resistance element storing a high resistance state or a low resistance state based on the polarity of voltage application in a non-volatile manner. The access element has a resistance value in an off-state in a certain voltage range that is ten time or more as high as that in a select state. A read/write circuit is formed on the semiconductor substrate and underlying the cell array for data reading and data writing in communication with the cell array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.