Semiconductor circuit, inverter circuit, semiconductor apparatus, and manufacturing method thereof
US7606082B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 14, 2006 |
| Grant date | Oct 20, 2009 |
| Priority date | — |
| Expiry date | Mar 13, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01J2217/49
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The semiconductor circuit includes a voltage-controlled semiconductor device (N)N, the resistance value of which is controllable with a high voltage, the drain terminal of the N can be connected to the gate terminal (control terminal) of an output semiconductor device (NO) via a resistor (R) or to a last output stage of the driver circuit, the source terminal of the N is connected to the emitter terminal of the NO, and the gate terminal of the N is connected to the collector terminal, which is the output terminal, of the NO. When the input terminal of the semiconductor circuit is at the Hi-level, the NO OFF. By connecting the output terminal of the NO to the high-potential-side of a high-voltage circuit disposed separately and the negative electrode of a control power supply (VDD) to the low-potential-side of the high-voltage circuit in the state, in which the NO is OFF, a desired high voltage is applied between the collector and emitter of the NO. Since a p-channel MOSFET (PD) is turned ON as the input terminal potential is changed over to the Lo-level and the high voltage is still being applied to the output terminal of the NO, the N is turned ON and the NO is brought into the ON…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.