Testing for SRAM memory data retention
US7606092B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 1, 2007 |
| Grant date | Oct 20, 2009 |
| Priority date | — |
| Expiry date | Nov 10, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/41
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of testing a memory cell includes generating a logic low signal, generating a logic high signal, reducing the logic high signal to a level corresponding to the logic low signal plus an offset to produce a reduced logic high signal, providing the logic low signal and the reduced logic high signal to a memory cell, allowing the memory cell to achieve a memory state, and testing the memory cell to determine if the memory state is an expected memory state. A memory array has an array of memory blocks, a write select circuit to provide write data to the array of memory blocks, and a data retention test circuit to reduce write data having a level corresponding to a logic high to a level corresponding to a logic low plus an offset.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.