Gate-level netlist reduction for simulating target modules of a design
US7606692B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 26, 2004 |
| Grant date | Oct 20, 2009 |
| Priority date | — |
| Expiry date | Apr 26, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for analyzing a circuit design in preparation for a simulation. The method generally includes the steps of (A) marking each of a plurality of modules between a target module of the modules and a top module of the modules in a hierarchy of the circuit design as a first type by traversing upward through the hierarchy starting from the target module, (B) marking each of the modules as a second type where a parent module of the modules is marked as the first type by traversing downward through the hierarchy starting from the top module and (C) marking each of the modules as a third type where the parent module is not marked as the keep type by traversing downward through the hierarchy starting from the top module.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.