Multi-level content addressable memory
US7606968B2 · kind B2 · utility
35Cited by
5References
20Claims
0Family size
Assignee
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Key dates
| Filing date | May 8, 2006 |
| Grant date | Oct 20, 2009 |
| Priority date | — |
| Expiry date | Jun 11, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-level content addressable memory (CAM) architecture compresses out much of the redundancy encountered in the search space of a single CAM, particularly for flow-based lookups in a network. Destination and source address may be associated with internal equivalence classes independently in one level of the multi-level CAM architecture, while flow-specific properties linking arbitrary classes of the destination and source addresses may be applied in a later level of the multi-level CAM.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.