Store instruction ordering for multi-core processor
US7606998B2 · kind B2 · utility
13Cited by
7References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 30, 2004 |
| Grant date | Oct 20, 2009 |
| Priority date | — |
| Expiry date | May 23, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3858
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for minimizing stalls in a pipelined processor is provided. Instructions in an out-of-order instruction scheduler are executed in order without stalling the pipeline by sending store data to external memory through an ordering queue.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.