Method of fabricating a semiconductor device incorporating a semiconductor constructing body and an interconnecting layer which is connected to a ground layer via a vertical conducting portion
US7608480B2 · kind B2 · utility
Assignees
Inventor
Key dates
| Filing date | Jul 20, 2007 |
| Grant date | Oct 27, 2009 |
| Priority date | — |
| Expiry date | Jul 20, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes metal foil to which a ground potential is applied, at a semiconductor constructing body provided on the metal foil and having a semiconductor substrate and a plurality of external connection electrodes provided on the semiconductor substrate. An insulating layer is provided around the semiconductor constructing body and has a thickness substantially equal to the semiconductor constructing body. An one upper interconnecting layer is provided on the semiconductor constructing body and insulating layer, and electrically connected to the external connection electrodes. A vertical conducting portion extends through the insulating layer and electrically connects the metal foil and upper interconnecting layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.