Automatic phase-detection circuit for clocks with known ratios
US7609092B2 · kind B2 · utility
3Cited by
1References
22Claims
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Key dates
| Filing date | Jan 23, 2008 |
| Grant date | Oct 27, 2009 |
| Priority date | — |
| Expiry date | Apr 17, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/08
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An automatic phase detection circuit for generating an internal synchronization signal when two clock input signals achieve a certain phase relationship. No external reference signal is required. The logic state of one clock is sampled on the active edge of the other clock and stored in a shift register. The content of the shift register is compared to a pre-defined signature and a sync signal is generated when the content matches the pre-defined signature. A mask register may be used to define which bits of the shift register and pre-defined signature are compared.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.