Comparator with low supply current spike and input offset cancellation
US7609093B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 3, 2007 |
| Grant date | Oct 27, 2009 |
| Priority date | — |
| Expiry date | Aug 3, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45396
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A current control circuit is coupled in parallel with the current paths of a differential comparator circuit to ensure that a substantially constant current is drawn from a current source during all operating phases of a comparator. The current control circuit is biased by a reference voltage, which is also used to bias a V− input terminal of the differential comparator circuit. The reference voltage is stored by a sample capacitor, which is charged by applying the reference voltage to a V+ input terminal of the differential comparator circuit while coupling an output terminal of the differential comparator circuit to the sample capacitor in a unity feedback configuration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.