Semiconductor memory device
US7609551B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 25, 2007 |
| Grant date | Oct 27, 2009 |
| Priority date | — |
| Expiry date | Mar 30, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6734
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This disclosure concerns a memory comprising a charge trapping film; a gate insulating film; a back gate on the charge trapping film; a front gate on the gate insulating film; and a body region provided between a drain and a source, wherein the memory includes a first storage state for storing data depending on the number of majority carriers in the body region and a second storage state for storing data depending on the amount of charges in the charge trapping film, and the memory is shifted from the first storage state to the second storage state by converting the number of majority carriers in the body region into the amount of charges in the charge trapping film or from the second storage state to the first storage state by converting the amount of charges in the charge trapping film into the number of majority carriers in the body region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.