On-chip circuitry for bus validation
US7610526B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 24, 2005 |
| Grant date | Oct 27, 2009 |
| Priority date | — |
| Expiry date | Jun 16, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31858
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Systems, methodologies, media, and other embodiments associated with validating a bus are described. One exemplary system embodiment includes an integrated circuit operably connectable to a bus, the bus being connectable to an external device configured to drive one or more electrical signals onto the bus. The integrated circuit may comprise a first logic configured to receive a test sequence of electrical signals from the bus, a second logic configured to produce a check sequence of electrical signals related to the test sequence of electrical signals, and a compare logic operably connected to the first logic and the second logic. The compare logic may be configured to determine whether the bus is correctly transmitting data based, at least in part, on comparing the test sequence and the check sequence.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.