Single spacer process for multiplying pitch by a factor greater than two and related intermediate IC structures
US7611980B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 30, 2006 |
| Grant date | Nov 3, 2009 |
| Priority date | — |
| Expiry date | Jan 19, 2027 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/947
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Single spacer processes for multiplying pitch by a factor greater than two are provided. In one embodiment, n, where n≧2, tiers of stacked mandrels are formed over a substrate, each of the n tiers comprising a plurality of mandrels substantially parallel to one another. Mandrels at tier n are over and parallel to mandrels at tier n−1, and the distance between adjoining mandrels at tier n is greater than the distance between adjoining mandrels at tier n−1. Spacers are simultaneously formed on sidewalls of the mandrels. Exposed portions of the mandrels are etched away and a pattern of lines defined by the spacers is transferred to the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.