Semiconductor device including a strained superlattice layer above a stress layer
US7612366B2 · kind B2 · utility
112Cited by
53References
33Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 13, 2006 |
| Grant date | Nov 3, 2009 |
| Priority date | — |
| Expiry date | Jul 13, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/8162
Abstract
A semiconductor device may include a stress layer and a strained superlattice layer above the stress layer and including a plurality of stacked groups of layers. More particularly, each group of layers of the strained superlattice layer may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.