Optimized memory addressing
US7612780B2 · kind B2 · utility
1Cited by
2References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 6, 2007 |
| Grant date | Nov 3, 2009 |
| Priority date | — |
| Expiry date | Jun 27, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1684
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present invention relate to accessing a first pair of adjacent data blocks using a first channel of a dual channel memory device; and simultaneously accessing a second pair of adjacent data blocks using a second channel of the memory device, the second pair being spaced apart from the first pair by a predetermined interval.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.