Two mask floating gate EEPROM and method of making
US7615436B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 20, 2004 |
| Grant date | Nov 10, 2009 |
| Priority date | — |
| Expiry date | May 19, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/00
Abstract
There is provided a floating gate transistor, such as an EEPROM transistor, and method of making the transistor using two masking steps. The method of making a transistor includes patterning a floating gate layer using a first photoresist mask to form a floating gate rail and doping an active area using the floating gate rail as a mask to form source and drain regions in the active area. The method also includes patterning a control gate layer, a control gate dielectric layer, the floating gate rail, a tunnel dielectric layer and the active area using a second photoresist mask to form a control gate, a control gate dielectric, a floating gate, a tunnel dielectric and a channel island region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.