Memory reset apparatus
US7616039B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 8, 2008 |
| Grant date | Nov 10, 2009 |
| Priority date | — |
| Expiry date | Jun 1, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/22
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A memory reset apparatus including a first inverse circuit, a logic circuit, and a plurality of second inverse circuits is provided. The first inverse circuit receives a control signal generated by a north bridge and generates a first signal, in which the control signal controls reset of a plurality of memories. The logic circuit performs a logic operation of the first signal and an indicating signal and generates a second signal, in which the indicating signal indicates each component of a computer system completely powered on. The plurality of second inverse circuits is respectively coupled between the logic circuit and the memories. The second inverse circuits inverse the second signal and respectively generate a plurality of reset signals to the memories, so as to reset the memories.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.