Lan Huang
14Patents
3h-index
11Co-inventors
53Inventor score
Filing activity: Dec 4, 2001 → Jan 2, 2014
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7286396B2 | Bit line selection transistor layout structure | Electricity | 4 | Expired |
| US9411771B2 | Server system for switching master and slave devices | Physics | 3 | Active |
| US7183608B2 | Memory array including isolation between memory cell and dummy cell portions | Electricity | 3 | Expired |
| US7839026B2 | Power discharge control system | Electricity | 2 | Active |
| US7403430B2 | Erase operation for use in non-volatile memory | Physics | 2 | Active |
| US7853810B2 | Core voltage controlling apparatus | Physics | 2 | Active |
| US8996850B2 | Server system and auto-reset method of the same | Electricity | 1 | Active |
| US6909131B2 | Word line strap layout structure | Electricity | 1 | Expired |
| US7616039B2 | Memory reset apparatus | Electricity | 1 | Active |
| US7064032B2 | Method for forming non-volatile memory cell with low-temperature-formed dielectric between word and bit lines, and non-volatile memory array including such memory cells | Electricity | 1 | Expired |
| US8045336B2 | Storage device backplane and identification circuit | Physics | 1 | Active |
| US8354335B2 | Apparatus and associated method for making a floating gate cell with increased overlay between the control gate and floating gate | Electricity | 0 | Active |
| US7879708B2 | Apparatus and associated method for making a floating gate cell with increased overlay between the control gate and floating gate | Electricity | 0 | Active |
| US6512710B1 | Reliability test method and circuit for non-volatile memory | Physics | 0 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.