Scalable bus structure
US7617343B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 2, 2005 |
| Grant date | Nov 10, 2009 |
| Priority date | — |
| Expiry date | Dec 22, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4265
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing system is disclosed with a sending component and a receiving component connected by a bus. The bus may be configured with transmit and receive channels. The transmit channel may have a plurality of sub-channels. The sending component may be configured to broadcast on each of the sub-channels information comprising read and write address locations, read and write control signals, and write data on each of the sub-channels. The receiving component may be configured to store the write data and retrieve read data in response to the information broadcast on any of the sub-channels, and broadcast the retrieved read data on the receive channel to the sending component. The sending component may further be configured to provide to the receiving component independent signaling for each of the sub-channels, the independent signaling being sufficient to allow the receiving component to determine the type of information broadcast on each of the sub-channels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.