Method and apparatus for detecting defects in integrated circuit die from stimulation of statistical outlier signatures
US7617427B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2005 |
| Grant date | Nov 10, 2009 |
| Priority date | — |
| Expiry date | Mar 13, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/303
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method and computer program for detecting and locating defects in integrated circuit die from stimulation of statistical outlier signatures includes receiving as input a test value of an electrical parameter measured for each of a plurality of identically designed electrical circuits, identifying one of the identically designed electrical circuits as an outlier for which the test value of the electrical parameter varies from a mean test value of the electrical parameter for the plurality of identically designed electrical circuits by at least a selected difference, monitoring the test value while subjecting a location on the outlier to a stimulus to detect a change in the test value as a function of the location, and generating as output the location for which the change in the test value is detected to identify a defect in the outlier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.