Processor event interface for programmable integrated circuit based circuit designs
US7617471B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 5, 2007 |
| Grant date | Nov 10, 2009 |
| Priority date | — |
| Expiry date | Oct 13, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/331
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of implementing a circuit design on a programmable integrated circuit can include displaying a list of at least one memory of the circuit design that is associated with the processor. A plurality of attributes of an event for the processor can be received. The plurality of attributes can specify a condition that, when met within at least one memory from the list, causes a signal to be generated to the processor. A description of an event interface for the processor can be automatically created according to the plurality of attributes of the interrupt. The description of the event interface can be incorporated into a description of the circuit design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.