DC balance compensation for AC-coupled circuits
US7620121B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 9, 2004 |
| Grant date | Nov 17, 2009 |
| Priority date | — |
| Expiry date | Nov 18, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/0276
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A receiver has a first input port and a second input port both coupled to a differential amplifier through first and second input capacitors. A bias circuit coupled to the core side of the first input capacitor and to the core side of the second input capacitor is configured to provide a selected voltage to at least one of the first input and the second input of the differential amplifier. In one embodiment, a common mode bias circuit provides a common mode voltage to both inputs of a differential amplifier. In a particular embodiment, a run length detector monitors the output of the differential amplifier and provides a run length feedback signal or an average bit density feedback signal to the set the selected voltage between periods of data reception.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.