Low power microprocessor cache memory and method of operation
US7620778B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 25, 2005 |
| Grant date | Nov 17, 2009 |
| Priority date | — |
| Expiry date | Jan 31, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0893
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques for processing transmissions in a communications (e.g., CDMA) system including the use of a digital signal processor. The digital signal processor includes a cache memory system and associates a plurality of cache memory match lines with addressable memory lines of an addressable memory. Each of the cache memory match lines associates with one of corresponding sets of the cache memory. The method and system maintain each of the cache memory match lines at a low voltage. Once the digital signal processor initiates a search of the cache memory for retrieving data from a selected one of the corresponding sets of the cache memory, a match line drive circuit drives one of the cache memory match lines from a low voltage to a high voltage. The selected one of the cache memory match lines corresponds to the selected one of the corresponding sets of the cache memory. The digital signal processor compares the selected one of the cache memory match lines to an associated one of the addressable memory lines. Following the comparison step, the process returns the one of the cache memory match lines to the low voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.