Controller for a processor having internal memory
US7620795B1 · kind B1 · utility
4Cited by
2References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 14, 2005 |
| Grant date | Nov 17, 2009 |
| Priority date | — |
| Expiry date | Aug 11, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3861
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatus and method for a microcontroller are described. The microcontroller includes a microprocessor having storage and bussing for accessing the storage. A portion of the bussing is coupled to hardwired operation codes, and a portion of the storage is for storing code. The hardwired operation codes are in part for placing the microprocessor into an exception handling mode. The exception handling mode includes reactivating the storage for execution of the code without having to reload the code therein.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.