Error correction code memory system with a small footprint and byte write operation
US7620875B1 · kind B1 · utility
27Cited by
6References
20Claims
0Family size
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Key dates
| Filing date | Mar 7, 2006 |
| Grant date | Nov 17, 2009 |
| Priority date | — |
| Expiry date | Jan 17, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, apparatus and program storage device that provides an error correction code memory system with a small footprint and byte write operation. A memory controller virtualizes the memory controller interface, multiplexes ECC data onto the same pins as data, and stores replicated ECC data structures interleaved with data in system memory. These mechanisms enable a range of very cost effective small memory subsystems that support ECC operation in a minimum of standard commodity memory devices. ECC encoding is provided to support efficient byte write operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.