Method and apparatus for circuit design closure using partitions
US7620927B1 · kind B1 · utility
9Cited by
12References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 15, 2006 |
| Grant date | Nov 17, 2009 |
| Priority date | — |
| Expiry date | Dec 7, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/347
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of implementing a circuit design can include selecting the circuit design to be implemented, wherein the circuit design comprises a plurality of partitions, and receiving a user input specifying a value of a partition property. The partition property can be associated with a selected one of the plurality of partitions of the circuit design. The method also can include performing an incremental implementation flow upon the circuit design for implementation by, at least in part, selectively modifying portions of a prior implementation of the selected partition in accordance with the value of the partition property.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.