Cache used both as cache and staging buffer
US7624235B2 · kind B2 · utility
46Cited by
5References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 30, 2006 |
| Grant date | Nov 24, 2009 |
| Priority date | — |
| Expiry date | Apr 6, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a cache comprises a data memory comprising a plurality of data entries, each data entry having capacity to store a cache block of data, and a cache control unit coupled to the data memory. The cache control unit is configured to dynamically allocate a given data entry in the data memory to store a cache block being cached or to store data that is not being cache but is being staged for retransmission on an interface to which the cache is coupled.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.