Ruchi Wadhawan
34Patents
12h-index
32Co-inventors
81Inventor score
Filing activity: Oct 18, 1995 → Mar 4, 2016
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8156275B2 | Power managed lock optimization | Physics | 196 | Active |
| US6324181A | Fibre channel switched arbitrated loop | Electricity | 137 | Expired |
| US7007095B2 | Method and apparatus for unscheduled flow control in packet form | Electricity | 74 | Expired |
| US7496695B2 | Unified DMA | Physics | 47 | Active |
| US7624235B2 | Cache used both as cache and staging buffer | Physics | 46 | Active |
| US6192071A | Detecting overequalization for adapting equalization and offset for data transmissions | Electricity | 44 | Expired |
| US7349399B1 | Method and apparatus for out-of-order processing of packets using linked lists | Electricity | 27 | Expired |
| US7680963B2 | DMA controller configured to process control descriptors and transfer descriptors | Physics | 20 | Active |
| US5715287A | Method and apparatus for dual purpose twisted pair interface circuit for multiple speed media in a network | Emerging Cross-Sectional Technologies | 16 | Expired |
| US7461190B2 | Non-blocking address switch with shallow per agent queues | Physics | 16 | Expired |
| US7698478B2 | Managed credit update | Electricity | 15 | Active |
| US6222876A | Detecting valid data patterns for adapting equalization gain and offset for data transmissions | Electricity | 12 | Expired |
| US7970970B2 | Non-blocking address switch with shallow per agent queues | Physics | 10 | Active |
| US8959270B2 | Interrupt distribution scheme | Emerging Cross-Sectional Technologies | 9 | Active |
| US8209446B2 | DMA controller that passes destination pointers from transmit logic through a loopback buffer to receive logic to write data to memory | Physics | 8 | Active |
| US6118815A | Adapting equalization gain and offset for data transmissions | Electricity | 7 | Expired |
| US6256320A | Dual clocks for network device | Electricity | 7 | Expired |
| US7512129B1 | Method and apparatus for implementing a switching unit including a bypass path | Electricity | 7 | Expired |
| US8631213B2 | Dynamic QoS upgrading | Physics | 6 | Active |
| US8032670B2 | Method and apparatus for generating DMA transfers to memory | Physics | 6 | Active |
| US7752366B2 | Non-blocking address switch with shallow per agent queues | Physics | 4 | Active |
| US8578079B2 | Power managed lock optimization | Physics | 4 | Active |
| US7808999B2 | Method and apparatus for out-of-order processing of packets using linked lists | Electricity | 4 | Active |
| US5793260A | Current controlled oscillator with voltage independent capacitance | Electricity | 4 | Expired |
| US8176257B2 | Cache used both as cache and staging buffer | Physics | 4 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.