Segmented pipeline flushing for mispredicted branches
US7624254B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 24, 2007 |
| Grant date | Nov 24, 2009 |
| Priority date | — |
| Expiry date | Aug 4, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3867
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor pipeline is segmented into an upper portion—prior to instructions going out of program order—and one or more lower portions beyond the upper portion. The upper pipeline is flushed upon detecting that a branch instruction was mispredicted, minimizing the delay in fetching of instructions from the correct branch target address. The lower pipelines may continue execution until the mispredicted branch instruction confirms, at which time all uncommitted instructions are flushed from the lower pipelines. Existing exception pipeline flushing mechanisms may be utilized, by adding a mispredicted branch identifier, reducing the complexity and hardware cost of flushing the lower pipelines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.