Clock aware placement
US7624366B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2006 |
| Grant date | Nov 24, 2009 |
| Priority date | — |
| Expiry date | Dec 7, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/392
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The layout of latches in a common clock domain is efficiently optimized to shrink the physical size of the domain while maintaining timing requirements. The latches are placed in a first layout preferably using quadratic placement, and a star object is built representing an interim clock structure. The latches are weighted based on wire distance from a source of the star object, and then re-placed using the weighting. The weighted placement and repartitioning may be iteratively repeated until a target number of bins is reached. The boundary of the latches in the final global placement is used to define a movebound for further detailed placement.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.