FinFET with sublithographic fin width
US7625790B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 26, 2007 |
| Grant date | Dec 1, 2009 |
| Priority date | — |
| Expiry date | Sep 13, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/011
Abstract
At least one recessed region having two parallel edges is formed in an insulator layer over a semiconductor layer such that the lengthwise direction of the recessed region coincides with optimal carrier mobility surfaces of the semiconductor material in the semiconductor layer for finFETs to be formed. Self-assembling block copolymers are applied within the at least one recessed region and annealed to form a set of parallel polymer block lines having a sublithographic width and containing a first polymeric block component. The pattern of sublithographic width lines is transferred into the semiconductor layer employing the set of parallel polymer block lines as an etch mask. Sublithographic width semiconductor fins thus formed may have sidewalls for optimal carrier mobility for p-type finFETs and n-type finFETs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.