Transistor including paramagnetic impurities and having anti-parallel ferromagnetic contacts

US7626236B2 · kind B2 · utility

Assignee

• Purdue Research Foundation · US

Inventors

• Supriyo Datta · West Lafayette, US
• Sayeef Salahuddin · Walnut Creek, US

Key dates

• Filing date: Jun 28, 2006
• Grant date: Dec 1, 2009
• Expiry date: Jan 19, 2027

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S977/936

Abstract

A transistor device may comprise a source having a first ferromagnetic contact thereto, a drain having a second ferromagnetic contact thereto, an electrically conductive gate positioned over a channel region separating the source and the drain, and an electrically insulating layer disposed between the gate and the channel region. The first and second ferromagnetic contacts have anti-parallel magnetic orientations relative to each other. The electrically insulating layer includes a number of paramagnetic impurities each having two spin states such that electrons interacting with the paramagnetic impurities cause the paramagnetic impurities to flip between the two spin states.