Implementing vector memory operations
US7627735B2 · kind B2 · utility
38Cited by
2References
28Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 21, 2005 |
| Grant date | Dec 1, 2009 |
| Priority date | — |
| Expiry date | Jul 9, 2026 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, the present invention includes an apparatus having a register file to store vector data, an address generator coupled to the register file to generate addresses for a vector memory operation, and a controller to generate an output slice from one or more slices each including multiple addresses, where the output slice includes addresses each corresponding to a separately addressable portion of a memory. Other embodiments are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.