External memory accessing DMA request scheduling in IC of parallel processing engines according to completion notification queue occupancy level
US7627744B2 · kind B2 · utility
10Cited by
27References
17Claims
0Family size
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Key dates
| Filing date | May 10, 2007 |
| Grant date | Dec 1, 2009 |
| Priority date | — |
| Expiry date | Dec 20, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3891
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit comprises an external memory, a plurality of parallel connected Vector Processing Engines (VPEs), and an External Memory Unit (EMU) providing a data transfer path between the VPEs and the external memory. Each VPE contains a plurality of data processing units and a message queuing system adapted to transfer messages between the data processing units and other components of the integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.