Semiconductor package with inner leads exposed from an encapsulant
US7629677B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2006 |
| Grant date | Dec 8, 2009 |
| Priority date | — |
| Expiry date | Aug 8, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18301
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided is a semiconductor package including a high integration semiconductor chip and having a minimum area to be mounted on a circuit board. The semiconductor package includes a semiconductor chip, a plurality of inner leads, and an encapsulant. The plurality of inner leads include upper and bottom surfaces and are electrically connected to the semiconductor chip. The encapsulant covers the semiconductor chip and the plurality of inner leads. The upper surfaces of the plurality of inner leads are fixed to the encapsulant, portions of the bottom surfaces of the plurality of inner leads are exposed from the encapsulant, and the bottom surfaces of the plurality of inner leads are disposed at a different height from a bottom surface of the encapsulant.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.