Delay stage, ring oscillator, PLL-circuit and method
US7629856B2 · kind B2 · utility
8Cited by
9References
52Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 27, 2006 |
| Grant date | Dec 8, 2009 |
| Priority date | — |
| Expiry date | Jan 20, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/0028
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay stage for a semiconductor device includes at least one delay branch and at least one controllable switching apparatus. The at least one controllable switching apparatus is configured to connect a predefined amount of the at least one delay branch to a supply voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.