Method for erasing data of NAND flash memory device
US7630255B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 29, 2007 |
| Grant date | Dec 8, 2009 |
| Priority date | — |
| Expiry date | Sep 18, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5621
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for erasing data of a NAND flash memory device including memory cell blocks may include using a first erase voltage applied to memory cells of a block to be erased. A first verification may be performed to verify erased states of the memory cells using a first verify voltage different than a second verify voltage. Memory cells that have not passed the first verification process are classified as a first group and a verification is performed on memory cells that have passed the first verification using the second verify voltage. Memory cells that have passed the second verification are classified as a second group and memory cells that have not passed the second verification are classified as a third group. Then data of the memory cells of the three groups are erased using first, second and third step voltages and first, second and third erase voltages, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.